Superscalar Processor Validation at the Microarchitecture Level 1

We describe a rigorous ATPG-like methodology for validating the branch prediction mechanism of the Pow-erPC604 which can be easily generalized and made applicable to other processors. Test sequences based on nite state machine (FSM) testing are derived from small FSM-like models of the branch prediction mechanism. These sequences are translated into PowerPC instruction sequences. Simulation results show that 100% coverage of the targeted functionality is achieved using a very small number of simulation cycles. Simulation of some real programs against the same targeted func-tionality produces coverages that range between 34% and 75% with four orders of magnitude more cycles. We also use mutation analysis to modify some func-tionality of the behavioral model to further illustrate the eeectiveness of our generated sequence. Simulation results show that all 54 mutants in the branch prediction functionality can be detected by measuring transition coverage.